CsF & RbF Electron-Selective Passivated Contacts for Crystalline Silicon Solar Cells (c-Si PV)

1) Overview and Technical Value

Crystalline silicon (c-Si) remains the most mature and widely deployed photovoltaic platform. The next efficiency gains increasingly depend on reducing carrier recombination and contact resistance at the c-Si/metal interface, while simplifying process complexity and lowering cost. Conventional architectures (e.g., direct metal contacts on lightly doped silicon in standard PERC) can suffer from interface defects, Fermi-level pinning, sizable Schottky barriers, and high recombination at the contact region.

A carrier-selective passivated contact addresses these losses by inserting an ultrathin stack between silicon and the electrode: a tunnel passivation layer (typically 1–10 nm) plus an electron-selective transport layer (typically 1–20 nm). In this approach, CsF and RbF (and closely related Cs/Rb halide/fluoride compounds) serve as electron-selective materials with low effective work function and large bandgap, enabling:

• Ohmic-like electron extraction with very low contact resistivity when properly engineered with the tunnel layer and metal stack
• Suppressed hole transport via a large valence-band barrier, improving selectivity and reducing recombination
• Lower parasitic optical absorption than many doped silicon layers used in traditional passivated-contact concepts
• Low-temperature processing compatibility (vacuum thermal evaporation or ALD), supporting higher throughput and simpler toolsets

2) Detailed Experimental / Process Workflow

Below is a step-by-step process flow. You can implement the electron-selective passivated contact as a front-end or rear-end structure. The core differentiator is the insertion of a CsF/RbF-based electron-selective transport layer on top of a tunnel passivation layer, deposited by vacuum thermal evaporation or ALD.

A. Substrate Preparation (c-Si wafer)

1. Wafer selection: choose crystalline silicon wafers per target architecture (commonly n-type for rear electron contact development). Typical thickness around 180 ± 20 μm.
2. Double-side texturing: perform alkaline texturing (e.g., KOH-based) to form light-trapping surface morphology.
3. Cleaning: conduct standard RCA cleaning, rinse with DI water, and dry (N2 blow and/or hot plate).

B. Front-Side Junction and Optical/Electrical Stack (example route)

1. Emitter formation: create the required front-side emitter (example: boron emitter using BBr3 source for a p+ emitter on n-Si), then remove unwanted diffusion at the rear/edges as needed.
2. Front surface passivation: deposit a passivation layer such as Al2O3 (e.g., ALD) with thickness in the ~10 nm class depending on optimization targets.
3. Anti-reflection coating: deposit SiNx or related ARC stack (typ. ~80 nm class, adjusted for optical design).
4. Front metallization: form the front electrode using screen-printed Ag paste and firing, or an alternative metallization route aligned with your process line.
5. Optional front-end electron-selective stack (if implementing the passivated electron contact on the front): deposit tunnel passivation + CsF/RbF layer first, then a transparent electrode (SnO2/ITO/IZO), then ARC, then metal grid.

C. Rear Electron-Selective Passivated Contact (CsF/RbF core)

1. Deposit tunnel passivation layer (1–10 nm) on the rear c-Si surface.
   • Common choices: SiOx (including LPCVD-grown ultrathin tunnel oxide), Al2O3, TiO2, ZnO, intrinsic a-Si:H, or intrinsic a-SiC:H.
   • Goal: reduce interface defect density and enable carrier tunneling while maintaining strong passivation.
2. Deposit electron-selective transport layer (1–20 nm) using CsF, RbF, or a controlled mixture/stack of cesium/rubidium compounds.
   • Method 1: Vacuum thermal evaporation
     • Load high-purity CsF/RbF source material into a compatible crucible/boat designed for fluoride salts.
     • Pump down to high vacuum (typical base pressure in the 10-4 Pa class, or as low as your tool allows).
     • Evaporate at a stable low rate suitable for sub-10 nm control (engineers often run in the ~0.01–0.05 nm/s class for ultrathin layers; tune per source/geometry).
     • Target thickness: start with 2–6 nm as an initial screening window, then map 1–20 nm for process window and contact optimization.
   • Method 2: ALD
     • Use an ALD process capable of forming uniform ultrathin fluoride layers or fluoride-containing compounds with precise thickness control.
     • Target thickness: 1–20 nm with sub-nm control for contact resistivity vs. passivation trade-off mapping.
   • Handling note: CsF and RbF are moisture-sensitive; minimize ambient exposure, use dry storage, and consider in-situ transfer when available.
3. Deposit rear metal electrode (200 nm–2 μm).
   • Use thermal evaporation or other compatible deposition to form the metal stack (e.g., Al primary contact layer plus Ag capping layer for conductivity and stability).
   • Typical engineering practice: deposit an initial Al layer (order 100 nm) followed by a thicker Ag layer (order 300 nm) where appropriate, then adjust to your line’s metallization strategy.
4. Optional post-deposition anneal to stabilize contact and reduce defects.
   • Run in inert atmosphere (N2) with a temperature window chosen to maintain ohmic behavior and passivation integrity.
   • In similar alkali-halide contact concepts, ohmic contact can remain stable up to a moderate temperature regime; validate your CsF/RbF stack with TLM after each anneal condition.

D. Device Characterization (R&D Checklist)

• J–V under standard illumination: extract Voc, Jsc, FF, and efficiency to quantify the benefit of electron-selective passivated contact insertion.
• TLM contact resistivity (ρc): map ρc versus CsF/RbF thickness (1–10 nm screening first, then widen).
• Work function / interface energetics: use XPS/UPS (or quasi in-situ measurements) on CsF/RbF/metal stacks to confirm low effective work function and metal “insensitivity” trends.
• Thermal stability: anneal matrix (e.g., stepped temperatures in N2) and re-measure ρc and device metrics.
• Optical parasitic absorption: confirm that the ultrathin CsF/RbF layer contributes minimal absorption compared with heavily doped silicon layers.

3) Comparison vs Traditional Approaches (Summary for Engineers)

Practically, the CsF/RbF pathway aims to combine the contact-quality advantages of passivated contacts with a simpler, lower-temperature deposition toolkit and a thin, optically benign electron-selective layer, improving both manufacturability and performance headroom.

4) Why CsF, RbF, and Related Cesium/Rubidium Compounds Are Advantageous Here

The electron-selective layer is the “workhorse” interface that controls band alignment, carrier selectivity, and contact resistivity. Selecting CsF and RbF (or engineered stacks/mixtures with other cesium/rubidium compounds) provides several practical advantages:

Raw Material Guidance (What R&D Teams Should Specify)

• Purity: specify high purity grades to minimize metal/oxide contamination that can degrade interface passivation and raise ρc.
• Moisture control: require low moisture content and moisture-barrier packaging; CsF/RbF are moisture-sensitive and should be handled in dry conditions.
• Thermal evaporation suitability: request particle size and morphology suitable for stable evaporation, minimizing spitting and thickness non-uniformity.
• Formulation options: consider CsF/RbF single layers, bilayers, or co-deposited mixtures to tune selectivity, stability, and interface energetics.
• Compatibility: verify compatibility with your tunnel passivation chemistry (SiOx, Al2O3, etc.) and downstream metallization/anneal steps.

The mentioned synthesis method references patent document number CN202410213422.0